The present invention relates to a bit by bit selectively and electrically erasable, programmable, non-volatile memory device (EEPROM). The use of a standard CMOS/SOI technology, i.e. without any specific technological stage, makes it possible to envisage the integration of such EEPROM memory cells into CMOS logic circuits without any modification of the production technology.
Electrically erasable, programmable, non-volatile memories have existed since the mid-1970""s (FLOTOX cell invented by INTEL). They are characterized by a manufacturing process having two polycrystalline silicon levels (floating gate and control gate), generally high erasing and programming voltagegs ( greater than 15 V) and a complex memory cell with an access transistor, a double gate transistor and an erasing zone with a very small gate oxide thickness (tunnel oxide).
For reasons of technological complexity and the large surface area of the memory cell, this type of product has evolved little as regards production volume and integration density. The maximum densities are approximately 256 Kbits. At the same time, EPROMs and more recently flash EPROMs have undergone a considerable economic development, as well as a rapid evolution towards high integration densities (nowadays greater than 16 Mbits). However, the need to integrate non-volatile memory functionalities on logic circuits very rapidly became apparent in the mid-1980""s, particularly with the introduction of the first microcontrollers. In order to rapidly reprogram these memory cells, it has been necessary to be able to electrically erase them, which has made the EEPROM more attractive than the EPROLM for this application. From the standpoint of operation between the memory zone and the logic circuit, it has proved useful to be able to erase the said memory cells selectively and independently of one another, so that an EEPROM has proved of greater interest than a flash EPROM. Finally, for process compatibility and production cost reasons, it is very advantageous to have a CMOS process permitting both the implementation of the EEPROM plane and the logic part with minimum technological modifications. This has led to the interest in single poly EEPROM cells, i.e. having a single polycrystalline silicon level. Numerous memory cells of this type have been disclosed in journals and scientific conferences in the field.
The article by J. I. Miyamoto et al entitled xe2x80x9cExperimental 5V only 256 kbits CMOS EEPROM with a high performance single polysilicon cellxe2x80x9d published in IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, 1986, pp 852-859 describes a memory cell having a single polycrystalline silicon level, which uses a N+ diffusion zone as the control gate and the single polycrystalline silicon level for the MOS gate of the logic part and for the floating gate of the EEPROM plane. Despite an interesting functionality and a current use of this type of memory cell in the implementation of integrated circuits, this type of memory cell is limited as regards the integration density, bearing in mind its large surface area (cell size approximately 100 xcexcm2 for a 1.2 xcexcm technology and 70 xcexcm2 for a 0.7 xcexcm technology). Moreover, as in double poly EEPROMs, this type of structure suffers from a tunnel oxide reliability problem linked with the large surface of the tunnel oxide zone. Finally, such a memory cell requires high programming voltages, as well as a special insulation of the N+ zone defining the control gate.
The article by K. Ohsaki et al entitled xe2x80x9cA single poly EEPROM cell structure for use in standard CMOS processxe2x80x9d published in IEEE Journal of Solid-State Circuits, vol. 29, No. 3, pp 311-316, 1994 describes another type of EEPROM cell, which also uses a single polycrystalline silicon level. Its special feature is the use of a CMOS process on conventional solid silicon (without specific technological stages), the memory cell being constituted by a MNOS transistor and a PMOS transistor, which are adjacent and, which have common gates. These gates are in fact floating gates. The inversion layer beneath the PMOS transistor, as well as the P+ S/D diffusion serve as a control gate. The source and drain zones of the NMOS transistor are connected to earth or ground. The size of the cell is more compact (31 xcexcm2 for 0.8 xcexcm design rules), but it suffers from a considerable minimum distance to be respected between the NMOS transistor and the PMOS transistor in order to avoid any latch-up risk. Finally, this memory cell has no selection transistor, as in the article by Miyamoto et al, and consequently requires either a collective reading of the memory cells, or a collective erasing.
French patent application 2 726 935 also describes a memory cell implemented in a SOI (silicon on insulator) structure. However, the technology used in this document corresponds to a solid silicon technology. Thus, insulation or isolation trenches are required for insulating the memory cells.
The present invention relates to a non-volatile memory cell, e.g. of the electrically bit by bit programmable and erasable EEPROM type and having the special feature of being conventionally implementable in a CMOS/SOI process. In addition, the memory cell surface area is preferably small.
More specifically, the invention relates to an electrically erasable, non-volatile memory device, having a memory cell of the floating gate type, defined by a source zone, a drain zone, a channel zone and a control gate zone, the latter being separated from the channel zone by an insulation zone, said five zones being implemented in a semiconductor film formed on an insulating layer, said memory cell being laterally insulated by one or more insulation zones in contact with the insulating layer.
The invention also relates to an electrically erasable, non-volatile memory device having, in a semiconductor film separated by an insulating layer from a substrate, at least one memory cell laterally insulated by insulation zones in contact with the insulating layer, said memory cell comprising a transistor, whose control gate is implemented by a diffusion zone in the semiconductor film, the floating gate being formed above a channel zone implemented in the semiconductor film between a source zone and a drain zone and above the control gate.
This device has a direct lateral insulation from the memory cell by insulation zones. It consequently requires no insulation trenches.
Moreover, the structure according to the invention only requires one semiconductor film of limited thickness, of a few tenths of a xcexcm (e.g. 0.1 to 0.3 xcexcm), which can be very advantageously compared with the thickness of 1 to 2 um required in the device described in FR-2 726 935.
The dielectric insulation of the components obtained as a result of the insulation zones is of a total nature and makes it possible to reduce to the minimum the insulation distance between the transistors, in a device having several memory cells.
According to a first embodiment, the insulation zones of the memory cell are implemented by a field oxide.
According to another embodiment, the insulation zones of the memory cell are implemented by the localized etching of the semiconductor film down to the insulating layer.
The storage device according to the invention solely uses transistors of a single conductivity type in the memory plane, no matter whether they are storage or selection transistors. This leads to a simplification in the production processes compared with a NMOS and PMOS memory cell requiring a dual N+ and P+ gate.
The total dielectric insulation of the control gate implemented in diffusion makes it possible to use a control voltage of random sign (positive or negative), as well as high control voltage values without any risk of latch-up or electric leaks.
A selection transistor can be used in conjunction with each memory cell. In particular, a selection gate of the selection transistor, connected to the information storage zone, permits the selection in writing, reading or erasing of only the considered memory cell.
A selection transistor can also be associated with a plurality of memory cells in order to permit the control and/or erasing of said plurality of memory cells.
The invention also relates to a process for implementing such a structure, comprising the following stages:
formation of a substrate by producing a semiconductor film on a stack formed by an electrically insulating layer and a support,
formation of an insulation zone in contact with the electrical insulating layer,
producing a channel zone and a control gate zone, by the successive doping of ions in the semiconductor film, said zones being insulated by the insulation zones,
producing a floating gate, above the channel zone and the control gate zone and insulated from the channel zone and the gate zone,
producing a drain zone and a source zone by doping ions in the semiconductor film on either side of the floating gate,
producing connections connected respectively to the drain zone, the source zone and the control gate zone.